Differences Between SMARC 2.1.1 and SMARC 2.2

Introduction to the SMARC Standard

SMARC (Smart Mobility ARChitecture) is a low-power, small-form-factor Computer-on-Module (COM) standard developed by SGET (Standardization Group for Embedded Technologies). It uses an MXM 3.0 314-pin connector and primarily targets ARM and low-power x86 platforms. It is widely used in:

• Industrial automation and edge computing
• Transportation and rail systems
• Medical devices
• Smart energy
• Smart buildings and IoT/IIoT

In the SMARC 2.x series, SMARC 2.1.1 has long been the mainstream stable version, while SMARC 2.2 (released in August 2024) represents a forward evolution with specification enhancements while maintaining full backward compatibility.

SMARC 2.1.1: The Mature and Stable Mainstream Version

SMARC 2.1.1 is a revision and refinement of earlier versions, featuring clear interface definitions and pin multiplexing rules. It supports mainstream ARM SoCs (e.g., NXP, Rockchip, TI, Qualcomm) and covers common high-speed and low-speed interfaces, including:

• PCIe (primarily Gen3)
• USB 2.0 / 3.0
• HDMI / eDP / LVDS
• I²S, I²C, SPI, UART
• GPIO

It has been widely adopted in industrial-grade products, forming a mature ecosystem with numerous carrier board designs.

SMARC 2.2: The Future-Oriented Enhanced Version

SMARC 2.2 does not overhaul 2.1.1 but introduces optional new interfaces and documentation fixes under full backward compatibility, making it better suited for next-generation SoCs. Key enhancements include:

• Added Support for SoundWire Audio Interface (Optional)
  • The original I²S2 audio interface can now be multiplexed with SoundWire.
  • Advantages: Lower power consumption, fewer pins, support for multi-device cascading, and better alignment with modern SoC audio subsystems.
  • Particularly valuable for smart terminals, human-machine interaction devices, and voice control systems.
• Enhanced PCIe Capabilities (Support for PCIe Gen4 Definitions)
  • Introduces PCIe Gen4 signal definitions and design considerations at the specification level (actual support depends on the SoC).
  • Reserves space for higher bandwidth, benefiting high-speed AI acceleration, NVMe storage, and industrial cameras.
  • Additionally, adds a SERDES Reset signal as a flexible alternative to PCIe Reset, improving initialization reliability for high-speed serial links.
• Improved Pin Definitions and Documentation Clarity
  • Corrects ambiguities and errors in earlier specifications.
  • Optimizes signal descriptions, multiplexing rules, and annotations (e.g., HDMI AC coupling details).
  • Significantly reduces design risks for carrier board developers and hardware engineers.
• Synchronized Update to the Design Guide
  • The v2.2 Design Guide (released in 2025) provides clearer serial debugging recommendations, improved USB-C/Type-C reference designs, and more practical implementation advice.
  • While not mandatory, it greatly enhances engineering feasibility.

SMARC 2.1.1 vs. SMARC 2.2 Comparison Table

Engineering and Product Selection Recommendations

• When to Choose SMARC 2.1.1:
  • Existing mature carrier board designs
  • Stable product lifecycle
  • No strong demand for PCIe Gen4 or modern audio architectures
• When to Choose SMARC 2.2:
  • New projects or platform development
  • Using next-generation SoCs like RK3588, RK3576, or NXP i.MX9
  • Requiring higher PCIe bandwidth or SoundWire audio
  • Desiring longer technical lifecycle for the carrier board

Conclusion

SMARC 2.2 is not a rejection of 2.1.1 but a "reinforcing upgrade" oriented toward the future: it preserves the existing ecosystem while proactively adapting to new SoC capabilities and improving specification rigor and implementability. For industrial and edge computing products, SMARC 2.2 offers greater long-term value, while SMARC 2.1.1 remains a reliable and mature choice.